DocumentCode :
2741167
Title :
Hazard-free synthesis and decomposition of asynchronous circuits
Author :
Chen, Ren-Der ; Jou, Jer Min ; Shiau, Yew-Horng
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
1999
fDate :
18-21 Jan 1999
Firstpage :
185
Abstract :
In this paper, we solve the problems of hazard-free synthesis and decomposition of asynchronous speed-independent circuits for technology mapping. All high fanin gates are decomposed into gates that can be implemented by the gate library. We first analyze the conditions where hazards may occur during decomposition and then give corresponding strategies to solve them. All the proposed algorithms have been implemented and applied to the asynchronous benchmarks to verify their correctness. Experimental results show that less area is required in our final implementations
Keywords :
Petri nets; asynchronous circuits; logic CAD; signal flow graphs; Petri net; asynchronous benchmarks; asynchronous speed-independent circuits; decomposition; gate library; hazard-free synthesis; high fanin gates; signal transition graph; technology mapping; Asynchronous circuits; Circuit synthesis; Delay; Hazards; Libraries; Signal analysis; Signal synthesis; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
Type :
conf
DOI :
10.1109/ASPDAC.1999.759991
Filename :
759991
Link To Document :
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