DocumentCode :
2741173
Title :
SLOTFET fabrication of self-aligned sub-100-nm fully-depleted SOI CMOS
Author :
Chen, C.K. ; Chen, C.L. ; Gouker, P.M. ; Wyatt, P.W. ; Yost, D.-R. ; Burns, J.A. ; Suntharalingam, V. ; Fritze, M. ; Keast, C.L.
Author_Institution :
Lincoln Lab., MIT, Lexington, MA, USA
fYear :
2000
fDate :
2000
Firstpage :
82
Lastpage :
83
Abstract :
In recent years, substantial efforts have been directed toward development of SOI CMOS circuits, with gate lengths scaled to the sub-100 nm regime. These efforts have been motivated by the potential of low voltage, low power, and high speed performance of SOI CMOS in comparison to bulk devices (Hu, 1998). In this work, we describe a new sub-100 nm CMOS SLOTFET fabrication process using conventional 0.25 μm SOI CMOS processing techniques with DUV 248 nm photolithography, and we present experimentally measured p- and n-MOSFET characteristics. In comparison to an existing fully-depleted 0.25 μm SOI CMOS process (Liu et al, 1998), the SLOTFET process offers several important advantages, including (i) self aligned T-gate, allowing lower gate resistance required for high-fmax RF transistors, (ii) island spacers, suppressing parasitic sidewall transistors, (iii) recessed SOI channel region, minimizing short-channel effects and drain-induced-barrier lowering (DIBL), and (iv) raised source-drain region, allowing the maximum advantage of a cobalt salicide process for low source-drain series resistance. In the first SLOTFET fabrication run, both p- and n-MOS devices exhibited very promising sub-threshold slopes, drive current, off-state leakage, and DIBL; fine tuning is needed to optimize drive current, threshold voltage, and series resistance
Keywords :
CMOS integrated circuits; MOSFET; electric resistance; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; leakage currents; nanotechnology; silicon-on-insulator; ultraviolet lithography; 0.25 micron; 100 nm; 248 nm; CMOS SLOTFET fabrication process; DIBL; DIBL minimization; DUV photolithography; RF transistors; SLOTFET fabrication; SLOTFET process; SOI CMOS circuits; SOI CMOS processing techniques; Si-SiO2; cobalt salicide process; drain-induced-barrier lowering; drive current; fully-depleted SOI CMOS process; gate length scaling; gate resistance; high speed performance; island spacers; low power performance; low voltage performance; n-MOSFET characteristics; off-state leakage; p-MOSFET characteristics; parasitic sidewall transistor suppression; raised source-drain region; recessed SOI channel region; self aligned T-gate; self-aligned fully-depleted SOI CMOS; series resistance; short-channel effects minimization; source-drain series resistance; sub-threshold slope; threshold voltage; CMOS process; CMOS technology; Cobalt; Electrical resistance measurement; Fabrication; Lithography; Low voltage; MOSFET circuits; Radio frequency; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2000 IEEE International
Conference_Location :
Wakefield, MA
ISSN :
1078-621X
Print_ISBN :
0-7803-6389-2
Type :
conf
DOI :
10.1109/SOI.2000.892780
Filename :
892780
Link To Document :
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