DocumentCode
2741222
Title
A scheduling method for synchronous communication in the Bach hardware compiler
Author
Sakurai, Ryoji ; Takahashi, Mizuki ; Kay, Andrew ; Yamada, Akihisa ; Fujimoto, Tetsuya ; Kambe, Takashi
Author_Institution
Design Technol. Dev. Center, Sharp Corp., Nara, Japan
fYear
1999
fDate
18-21 Jan 1999
Firstpage
193
Abstract
In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from a behavioral Bach-C description and statically prescheduled to synchronize communications between threads if possible. Then all the operations and communications of each thread are synthesized independently according to the prescheduling result. Consequently, we can synthesize large system LSIs efficiently, because we do not need to synthesize the whole system descriptions at once to synchronize communications. Experimental results show that our method improves throughput of synthesized circuits and is applicable to large systems designed with the Bach hardware compiler
Keywords
circuit layout CAD; communication complexity; hardware description languages; high level synthesis; large scale integration; logic partitioning; sequential circuits; Bach hardware compiler; behavioral Bach-C description; high-speed circuit; large system LSI; prescheduling; scheduling method; synchronous communication between threads; throughput of synthesized circuits; Algorithm design and analysis; Circuit synthesis; Clocks; Control system synthesis; Costs; Hardware; Large-scale systems; Scheduling; Timing; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location
Wanchai
Print_ISBN
0-7803-5012-X
Type
conf
DOI
10.1109/ASPDAC.1999.759993
Filename
759993
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