Title :
Comparison of 0.25 μm bulk, PD and FD SOI CMOS implementations of a low-voltage low-power programmable DLL for linear delay generation
Author :
Delatte, P. ; Brodéoux, V. ; Lorent, Ph ; Flandre, D.
Author_Institution :
Lab. for Microelectron., Katholieke Univ., Leuven, Belgium
Abstract :
This paper describes the SOI implementation of a low-voltage low-power programmable delay locked loop (DLL) for linear delay generation in graphics display applications. In order to achieve the best linearity performance, a new scale structure with programmable delay stages is introduced. Since a programmable stage increases the complexity and thus the minimum achievable delay, a high performance technology is required to implement the target specifications. Simulation results in 0.25 μm bulk, partially-depleted (PD) and fully-depleted (FD) SOI CMOS are compared and experimental results are reported for the most promising FD process
Keywords :
CMOS integrated circuits; computer displays; computer graphic equipment; delay lock loops; low-power electronics; programmable circuits; silicon-on-insulator; 0.25 micron; DLL; FD SOI CMOS implementation; FD process; PD CMOS implementation; SOI implementation; Si-SiO2; bulk CMOS implementation; circuit complexity; fully-depleted SOI CMOS; graphics display applications; linear delay generation; linearity performance; low-voltage low-power programmable DLL; low-voltage low-power programmable delay locked loop; minimum achievable delay; partially-depleted SOI CMOS; programmable delay stages; scale structure; simulation; target specifications; CMOS technology; Circuit simulation; Delay effects; Delay lines; History; Inverters; Linearity; Phase frequency detector; Virtual colonoscopy; Voltage control;
Conference_Titel :
SOI Conference, 2000 IEEE International
Conference_Location :
Wakefield, MA
Print_ISBN :
0-7803-6389-2
DOI :
10.1109/SOI.2000.892785
