The implementation of hardware neural net systems

Author

Myers, D.J. ; Brebner, G.E.

Author_Institution

British Telecom Res. Lab., Ipswich, UK

fYear

1989

fDate

16-18 Oct 1989

Firstpage

57

Lastpage

61

Abstract

Describes a multilayer pipelined digital architecture suitable for the implementation of large neural nets (LN) for vision applications. It can also be used to do some pre-filtering, such as pixel averaging, by setting weight values appropriately. A 1024 node processor with a clock rate of 10 MHz can operate on an input vector consisting of 32×32 8 bit pixels in 102 μs. It can therefore process a 256×256 pixel frame in about 6.5 ms, which is well within the requirement for real-time processing, given a frame update rate of 20 ms. The architecture is currently being assessed to see how it can be extended to perform other image processing applications, and other NN training algorithms

Keywords

computer vision; computerised picture processing; hierarchical systems; neural nets; pipeline processing; 10 MHz; 102 mus; 1024 pixels; 20 ms; 256 pixels; 32 pixels; 6.5 ms; 65536 pixels; clock rate; computer vision; hardware neural net systems; multilayer pipelined digital architecture; picture processing; pixel averaging; pre-filtering; real-time processing; training algorithms;

fLanguage

English

Publisher

iet

Conference_Titel

Artificial Neural Networks, 1989., First IEE International Conference on (Conf. Publ. No. 313)

Conference_Location

London

Type

conf

Filename

51930