Symbolic layout techniques for ASIC design

Techniques are introduced for symbolic layout of ASICs (application-specific integrated circuits). These techniques, which include automatic layout generation, automatic technology update, hierarchical compaction, and symbolic cell library utilization, provide many desirable advantages for ASIC layout. Paradigms of these techniques are illustrated. Some automatic layout styles such as gate matrix, transistor chaining, and metal-metal matrix, are surveyed and tested with real circuits. Area efficiency, algorithmic complexity and electrical properties of these layout styles are analyzed. Comparisons and qualitative characterizations of these approaches are presented