DocumentCode
2741506
Title
A timing-driven block placer based on sequence pair model
Author
Huang, Gang ; Hong, Xianlong ; Qiao, Changge ; Cai, Yici
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
1999
fDate
18-21 Jan 1999
Firstpage
249
Abstract
In this paper, an effective timing-driven building block placer is proposed. Interconnection delay is modeled and included during the placing process in order to minimize the area and wirelength, as well as to satisfy the timing constraints in the algorithm. The simulated annealing technique for constrained optimization problem and the sequence pair model proposed by H. Murata et al. (1996) are applied. Not only the timing constraint but also the aspect ratio is taken into account in the search process. The experimental results demonstrate the algorithm can improve the timing delay and obtain good placement
Keywords
VLSI; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; simulated annealing; timing; NP-hard problem; VLSI; algorithm timing constraints; aspect ratio; building block placer; constrained optimization problem; floorplanning; goal function; interconnection delay; search process; sequence pair model; simulated annealing; timing delay; timing-driven block placer; Capacitance; Delay effects; Delay estimation; Integrated circuit interconnections; Latches; Pins; Simulated annealing; Stochastic processes; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location
Wanchai
Print_ISBN
0-7803-5012-X
Type
conf
DOI
10.1109/ASPDAC.1999.760007
Filename
760007
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