Title :
Data path synthesis for BIST with low area overhead
Author :
Li, Xiaowei ; Cheung, Paul Y S
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong
Abstract :
This paper presents an attempt towards design quality improvement by incorporating of self-testability features during data path (high-level) synthesis. This method is based on the use of test resource sharing possibilities to improve the self-testability of the circuit. This is achieved by incorporating testability constraints during register assignment. Experimental results are presented to demonstrate the effectiveness of the proposed data path synthesis for BIST approach
Keywords :
built-in self test; high level synthesis; logic testing; minimisation; BIST; data path; data path synthesis; low area overhead; register assignment; self-testability; testability constraints; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Delay; High level synthesis; Logic testing; Registers; Resource management; Test pattern generators;
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
DOI :
10.1109/ASPDAC.1999.760012
