An adaptive BIST to detect multiple stuck-open faults in CMOS circuits

Author

Rahaman, Hafijur ; Das, Debesh K. ; Bhattacharya, Bhargab B.

Author_Institution

Dept. of Electr. Eng., A.P.C. Roy Polytech., Calcutta, India

fYear

1999

fDate

18-21 Jan 1999

Firstpage

287

Abstract

Design of an adaptive built-in-self-test (BIST) scheme for detecting multiple stuck-open faults in a CMOS complex cell is proposed. The test pattern generator (TPG) adaptively generates a subset of single-input-change (SIC) test pairs based on the past responses of the circuit under test (CUT). The design is universal, i.e., independent of the structure and functionality of the CUT. The average length of the test sequence (TS) in an n-input CUT is (n+1).2ⁿ [(n+1).2^n-1] in a fault-free [faulty] condition. The response analyzer (RA) is also simple to design. All robustly testable multiple stuck-open faults (occurring simultaneously both in n- and p-parts) can be detected using the proposed BIST scheme

Keywords

CMOS digital integrated circuits; adaptive systems; automatic test pattern generation; built-in self test; design for testability; fault diagnosis; logic design; logic testing; BIST; CMOS circuits; adaptive BIST; adaptive built-in-self-test; average length; fault-free condition; multiple stuck-open faults; n-input CUT; response analyzer; robustly testable faults; test pattern generator; test sequence; Built-in self-test; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Robustness; Silicon carbide; TV; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.760015

Filename

760015