A method for evaluating upper bound of simultaneous switching gates using circuit partition

Author

Zhang, Kai ; Shinogi, Tsuyoshi ; Takase, Haruhiko ; Hayashi, Terunune

Author_Institution

Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan

fYear

1999

fDate

18-21 Jan 1999

Firstpage

291

Abstract

This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. Experimental results for ISCAS circuits show that the method efficiently evaluates the upper bounds of switching gates

Keywords

CMOS logic circuits; VLSI; combinational circuits; integrated circuit interconnections; logic partitioning; CMOS; ISCAS circuits; VLSI; circuit partition; combinational circuits; interconnections; maximum switching gates; simultaneous switching gates; upper bound; Capacitance; Combinational circuits; Genetic algorithms; Integrated circuit interconnections; Large scale integration; Power dissipation; Statistics; Switching circuits; Upper bound; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific

Conference_Location

Wanchai

Print_ISBN

0-7803-5012-X

Type

conf

DOI

10.1109/ASPDAC.1999.760016

Filename

760016