Decoupling capacitance study and optimization method for high-performance VLSIs

Author

Zhu, Q.K. ; Yong, J. ; Mozdzen, T.

Author_Institution

Chameleon Syst. Inc., Castro Valley, CA, USA

fYear

2010

fDate

14-16 April 2010

Firstpage

388

Lastpage

392

Abstract

Decoupling capacitance is necessary to stabilize the power distribution network due to the reduced supply voltage and increased current transitions. Decoupling capacitance planning should be a part of design tasks to minimize the silicon area while maintaining the stability of the power distribution network. This paper shows our study in the on-chip and on-package decoupling capacitors in high-performance microprocessors. At the end, we describe a computer algorithm to optimize the decoupling capacitance allocation based on the power grid analysis.

Keywords

VLSI; microprocessor chips; decoupling capacitance allocation; high-performance VLSI; microprocessors; on-chip decoupling capacitors; on-package decoupling capacitors; optimization method; power distribution network; power grid analysis; Capacitance; Capacitors; Grid computing; Microprocessors; Optimization methods; Power system stability; Power systems; Silicon; Very large scale integration; Voltage; Decoupling capacitance allocation; Microprocessor; Power distribution; Power grid analysis; SOC; VLSI design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Conference_Location

Vienna

Print_ISBN

978-1-4244-6612-2

Type

conf

DOI

10.1109/DDECS.2010.5491746

Filename

5491746