Title :
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes
Author :
Wu, F. ; Dilillo, L. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Ma, J. ; Zhao, W. ; Tehranipoor, M. ; Wen, X.
Author_Institution :
Dept. of Microelectron., Univ. of Montpellier II, Montpellier, France
Abstract :
At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS not only exhibits higher performance in coverage but also does not require as much extra power as predicted, especially in terms of peak power. These facts may represent convincing arguments for its wider use and development.
Keywords :
CMOS integrated circuits; boundary scan testing; fault diagnosis; integrated circuit testing; logic testing; power consumption; CMOS technology scaling; LOC testing scheme; LOS testing scheme; at-speed scan testing; launch-off-capture; launch-off-shift; test power consumption; transition fault coverage; CMOS technology; Circuit faults; Circuit testing; Clocks; Delay; Energy consumption; Lab-on-a-chip; Logic testing; Power supplies; System testing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location :
Vienna
Print_ISBN :
978-1-4244-6612-2
DOI :
10.1109/DDECS.2010.5491748
