Fault diagnosis of crosstalk induced glitches and delay faults

With the scaling of feature sizes into Deep-Submicron (DSM) values and ever increasing operating frequencies, chip failures due to crosstalk noise have become a major concern for circuit designers. It is essential that these faults be accurately diagnosed and affected wires re-routed to avoid possible chip failures. In this paper a new diagnostic fault simulator is described that diagnoses crosstalk induced glitch and delay faults in combinational circuit using information from fault simulation of single stuck-at faults. A realistic crosstalk fault model is used to insert crosstalk glitch and delay effects on a victim wire. The model considers the logical values of all possible time-compatible aggressors with those of the victim to insert the various noise effects. Once the design is found to be defective potential candidate wires are shortlisted by considering the fan-in cone of the faulty outputs. Further localization of fault site is performed by considering the logic states of candidate wires and their aggressors for the applied pattern pair. Experimental results on ISCAS´85 benchmark circuit for the given approach show that the method achieves high accuracy in localizing the crosstalk fault sites with good diagnostic resolution.