DocumentCode :
2742157
Title :
Synthesizing multiplier in reversible logic
Author :
Offermann, Sebastian ; Wille, Robert ; Dueck, Gerhard W. ; Drechsler, Rolf
Author_Institution :
Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
fYear :
2010
fDate :
14-16 April 2010
Firstpage :
335
Lastpage :
340
Abstract :
In the past, reversible logic has become an intensely studied research topic. This is mainly motivated by its applications in the domain of low-power design and quantum computation. Since reversible logic is subject to certain restrictions (e.g. fanout and feedback are not allowed), traditional synthesis methods are not applicable and specific methods have been developed. In this paper, we focus on synthesis of multiplier circuits in reversible logic. Three methods are presented that address the drawbacks of previous approaches. In particular, the large number of circuit lines in the resulting realizations as well as the poor scalability. Finally, we compare the results to circuits obtained by general purpose synthesis approaches.
Keywords :
logic design; low-power electronics; quantum computing; low-power design; multiplier circuit synthesis; quantum computation; reversible logic; Application software; Boolean functions; CMOS logic circuits; CMOS technology; Circuit synthesis; Computer science; Costs; Feedback; Logic circuits; Quantum computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location :
Vienna
Print_ISBN :
978-1-4244-6612-2
Type :
conf
DOI :
10.1109/DDECS.2010.5491757
Filename :
5491757
Link To Document :
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