Test pattern generation for the combinational representation of asynchronous circuits

In this paper we propose a new deterministic automatic test pattern generator (ATPG) for the stuck-at faults of the combinational representation (CR) of asynchronous sequential digital circuits (ASDCs). The modified FAN algorithm is applied to this CR to generate the test patterns. The FAN was extended to handle the complex gates and to be able to work with the CR of ASDCs. The ATPG was tested over a set of benchmark circuits. The test patterns from the presented ATPG will be used in the future to generate the sequence of test patterns for the ASDCs.