A hardware accelerated framework for the generation of design validation programs for SMT processors

In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. The two major characteristics of the proposed framework are an effective method to gather information about the processor internal status via its emulation, and an efficient algorithm which exploits these pieces of information for a generation process which is particularly suited for SMT processors. Performance counters (PCs) as well as ad hoc registers are used to achieve the former result, while a feedback-based generation process is devised to achieve the latter. Experimental results gathered on a real complex design (the OpenSPARC™ T1 core) show that the proposed framework can achieve high quality results with acceptable CPU time and human effort requirements.