Title :
Synthesis of online testable reversible circuit
Author :
Kole, Dipak Kumar ; Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Author_Institution :
Inf. Technol. Deptartment, Bengal Eng. & Sc. Univ., Shibpur, India
Abstract :
This article presents a technique for online fault detection under single missing-gate fault (SMGF) model in the reversible circuits. It is shown that in an (n × n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line with no garbage output yields an easily online testable design. The testable design is compared with the testable design proposed earlier in terms of extra control input and garbage outputs.
Keywords :
fault diagnosis; logic design; logic gates; k-CNOT gates; online fault detection; online testable reversible circuit synthesis; single missing-gate fault model; CMOS technology; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Logic circuits; Logic design; Logic gates; Logic testing; Quantum computing; Missing gate; Online Test; Reversible logic; low power;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location :
Vienna
Print_ISBN :
978-1-4244-6612-2
DOI :
10.1109/DDECS.2010.5491768
