DocumentCode
2742504
Title
Instruction set extensions for multi-threading in LEON3
Author
Danek, M. ; Kafka, L. ; Kohout, L. ; Sykora, J.
Author_Institution
Dept. of Signal Process., UTIA AV CR, Prague, Czech Republic
fYear
2010
fDate
14-16 April 2010
Firstpage
237
Lastpage
242
Abstract
This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems.
Keywords
embedded systems; field programmable gate arrays; instruction sets; microprocessor chips; multi-threading; LEON3 SPARCv8 processor; Xilinx Virtex2Pro FPGA; cache controller block; embedded systems; field programmable gate array; instruction set extensions; microthreading; multithreading; register file block; thread scheduler block;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location
Vienna
Print_ISBN
978-1-4244-6612-2
Type
conf
DOI
10.1109/DDECS.2010.5491777
Filename
5491777
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