DocumentCode :
2742552
Title :
Design methodology for over 100MFLOPS 64bit MPU with 0.8/spl mu/m BiCMOS technology
Author :
Nakakura, Y. ; Yoshida, T. ; Nakano, H. ; Nakajima, M. ; Goi, Y. ; Nakai, Y. ; Segawa, R. ; Kishida, T. ; Kameyama, S. ; Kadota, H.
Author_Institution :
Matsushita Electric Industrial Co.,Ltd.
fYear :
1991
fDate :
May 30 1991-June 1 1991
Firstpage :
21
Lastpage :
22
Keywords :
BiCMOS integrated circuits; Circuit simulation; Computer architecture; Decoding; Design methodology; Driver circuits; Pipelines; Reduced instruction set computing; Registers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1991. Digest of Technical Papers. 1991 Symposium on
Conference_Location :
Oiso, Japan
Type :
conf
DOI :
10.1109/VLSIC.1991.760059
Filename :
760059
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2742552
