Title :
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies
Author :
Gradzki, Jacek ; Borejko, Tomasz ; Pleskacz, Witold A.
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Warsaw, Poland
Abstract :
In this paper a comparison of two low noise amplifiers (LNAs) designed in two 90 nm CMOS technologies (so called A and B) has been made. For each technology two LNA topologies were simulated: inductively degenerated cascode (LC), which achieves high gain and low noise figure (NF), and folded cascode (FC), which can work with low supply voltage. These amplifiers were designed for a GPS/Galileo receiver. Chosen circuits demonstrate gains of 16.42 dB, 17.27 dB, 14.51 dB and 14.41 dB, consuming currents 2.492 mA, 3.093 mA, 2.834 mA and 4.609 mA with NFs equal to 1.881 dB, 1.914 dB, 2.345 dB and 2.427 dB for LC and FC architecture in A and B technologies respectively. For all amplifiers the supply voltage is 0.6 V.
Keywords :
CMOS integrated circuits; Global Positioning System; low noise amplifiers; CMOS technologies; GPS-Galileo receiver; current 2.492 mA; current 2.834 mA; current 3.093 mA; current 4.609 mA; folded cascode; gain 14.41 dB; gain 14.51 dB; gain 16.42 dB; gain 17.27 dB; inductively degenerated cascode; low noise amplifiers; low voltage LNA architectures; multistandard GNSS; noise figure; noise figure 1.881 dB; noise figure 1.914 dB; noise figure 2.345 dB; noise figure 2.427 dB; voltage 0.6 V; CMOS technology; Circuit simulation; Circuit topology; Gain; Global Positioning System; Low voltage; Low-noise amplifiers; Noise figure; Noise measurement; Satellite navigation systems;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
Conference_Location :
Vienna
Print_ISBN :
978-1-4244-6612-2
DOI :
10.1109/DDECS.2010.5491783
