Title :
Cell-Plate Line Connecting Complementary Bitline (c/sup 3/) Architecture For Battery Operating DRAMs
Author :
Asakura, M. ; Arimoto, K. ; Hidaka, H. ; Fujishima, Kenzaburo
Author_Institution :
Mitsubishi Electric Corp.
fDate :
May 30 1991-June 1 1991
Keywords :
Batteries; Capacitors; Joining processes; Laboratories; Large scale integration; Power supplies; Random access memory; Research and development; Signal to noise ratio; Voltage;
Conference_Titel :
VLSI Circuits, 1991. Digest of Technical Papers. 1991 Symposium on
Conference_Location :
Oiso, Japan
DOI :
10.1109/VLSIC.1991.760077
