• DocumentCode
    2743070
  • Title

    Self-Adaptive mechanism for cache memory reliability improvement

  • Author

    Agnola, Liviu ; Vladutiu, Mircea ; Udrescu, Mihai

  • Author_Institution
    Dept. of Comput. Sci., Politeh. Univ. Timisoara, Timisoara, Romania
  • fYear
    2010
  • fDate
    14-16 April 2010
  • Firstpage
    117
  • Lastpage
    118
  • Abstract
    This paper proposes a graceful degradation method applied to k-way set associative cache memories. The method is called “Self Adaptive cache Memories” (SAM); it works by removing the faulty locations from use, while reorganizing the memory to maintain a high performance. For the proposed contribution, the analysis provided herein reveals a significant reliability increase for the cache memory, while the entailed overhead remains small in comparison with the attained goals.
  • Keywords
    cache storage; circuit reliability; content-addressable storage; cache memory reliability improvement; self adaptive cache memories; way set associative cache memories; Analytical models; Cache memory; Hardware; Network topology; Power cables; Signal analysis; Space exploration; Testing; Vehicles; Virtual prototyping; BIST; cache; graceful degradation; reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on
  • Conference_Location
    Vienna
  • Print_ISBN
    978-1-4244-6612-2
  • Type

    conf

  • DOI
    10.1109/DDECS.2010.5491807
  • Filename
    5491807