DocumentCode
274327
Title
A model for comparing synchronization strategies for parallel logic-level simulation
Author
Bailey, M.L. ; Snyder, L.
Author_Institution
Dept. of Comput. Sci., Arizona Univ., Tucson, AZ, USA
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
502
Lastpage
505
Abstract
The authors apply a formal model described by M.L. Bailey and L. Snyder (Distributed Simulation, SCS, 1989, p.157-63) to the more difficult problem of comparing three different synchronization strategies: synchronous, conservative asynchronous, and optimistic asynchronous. They show that with unlimited processors, for variable-delay and unit-delay timing, conservative>
Keywords
circuit analysis computing; delays; logic testing; parallel algorithms; synchronisation; conservative asynchronous; optimistic asynchronous; parallel logic-level simulation; synchronization strategies; unit-delay timing; unlimited processors; variable-delay; Circuit simulation; Clocks; Computational modeling; Computer science; Computer simulation; Delay; Discrete event simulation; Parallel processing; Synchronization; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.77000
Filename
77000
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