A new two-dimensional systolic array for image processing and neural network applications

Summary form only given. A new type of high-performance VLSI systolic array is considered that is able to perform two-dimensional convolution with kernels sized larger than the physical array of processing elements. This array is particularly well-suited for neural network image processing algorithms that use large connected neighborhoods to model the transformations between layers of neurons. This array can also perform the two-dimensional convolution with the small kernels that are often used in standard image processing. In addition, the array can perform one-dimensional convolution and matrix-vector multiplication. The interface of the array to external memory is designed such that a conventional linear memory architecture is used for accessing and storing data. No variable-length scan conversion shift registers are needed by the systolic array to access an image stored in a conventional raster-scan format. The VLSI array is extensible so that both a single-chip and a multiple-chip architecture system can be built