Title :
PACE2: an improved parallel VLSI extractor with parameter extraction
Author :
Belkhale, K.P. ; Banerjee, P.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
An algorithm, PACE2, is described which is targeted to the second phase of extraction, called the parameter extraction phase. The authors have interfaced two models for resistance and capacitance. They propose a different partitioning scheme, namely, by equal number of rectangles, so as to balance the load. The parallel algorithm has been implemented on the Intel iPSC2/D4-MX hypercube.<>
Keywords :
VLSI; circuit layout CAD; parallel algorithms; Intel iPSC2/D4-MX hypercube; PACE2; capacitance; parallel VLSI extractor; parallel algorithm; parameter extraction; partitioning; resistance; Capacitance; Circuits; Concurrent computing; Hypercubes; Parallel algorithms; Parallel processing; Parameter extraction; Strips; Switches; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.77005
