Noise determination of a current conveyor in an inverting voltage amplifier configuration

Author

Siskos, S.

Author_Institution

Phys. Dept., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

fYear

2010

fDate

14-16 April 2010

Firstpage

12

Lastpage

15

Abstract

Analysis concentrated on noise performance issues of a CMOS high gain second generation current conveyor (CCII∞) is presented using both simulations and measurements results. The circuit has been fabricated in a 0.35 μm CMOS process by Austria Mikro Systeme (AMS) and it is examined analytically in terms of the noise contribution of each transistor in an inverting voltage amplifier configuration. Preliminary results about the noise minimization procedure are extracted. Regarding the topology performance characteristics, the power consumption is 93 μW and the total input referred rms noise is equal to 7.03 μV for a bandwidth of 1 Hz to 100 kHz.

Keywords

CMOS integrated circuits; amplifiers; current conveyors; Austria Mikro Systeme; CMOS high gain second generation current conveyor; bandwidth 1 Hz to 100 kHz; inverting voltage amplifier configuration; noise determination; noise minimization procedure; power 93 muW; size 0.35 mum; voltage 7.03 muV; Analytical models; Circuit noise; Circuit simulation; Current measurement; Gain measurement; Noise generators; Noise measurement; Performance analysis; Performance gain; Voltage; CMOS; inverting voltage amplifier; noise analysis; second generation high gain current conveyor;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium on

Conference_Location

Vienna

Print_ISBN

978-1-4244-6612-2

Type

conf

DOI

10.1109/DDECS.2010.5491826

Filename

5491826