Title :
A grouping heuristic algorithm for gate matrix layout
Author :
Liu, Jongping ; Lai, Faipei
Author_Institution :
Dept. of Comput. Sci., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
For the gate matrix layout problem, it is necessary to minimize the area of the layout and the total wire length. The authors propose grouping poly-gates as a pseudo gate to simplify the problem and reduce execution time. Good results have been obtained very quickly using the grouping insertion
Keywords :
application specific integrated circuits; circuit layout CAD; logic CAD; execution time; gate matrix layout; grouping heuristic algorithm; grouping insertion; poly-gates; total wire length; Computer science; Costs; Delay; Heuristic algorithms; Logic circuits; Simulated annealing; Wire;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68625
