DocumentCode
2743739
Title
A New Lock-Detect Circuit for Self Correcting DLLs
Author
Ghaffari, A. ; Abrishamifar, A.
Author_Institution
Dept. of Electr. Eng., Iran Univ. of Sci. & Technol., Tehran
fYear
2006
fDate
6-8 Sept. 2006
Firstpage
1
Lastpage
4
Abstract
This paper describes a new architecture for lock-detect circuit that is used in self correcting DLLs. Using this architecture solves the false locking problem of conventional DLLs. The operation of proposed architecture does not depend on the duty cycle of the input phases. The proposed lock-detect circuit is used in a wide frequency range and low jitter delay-locked loop. The circuit design and ADS simulation are based upon TSMC 0.18 mum CMOS process. The simulation results show that the proposed DLL has a wide locking range from 120 to 420 MHz. Moreover rms jitter is as low as 1.2 ps at 420 MHz
Keywords
CMOS digital integrated circuits; delay lock loops; 0.18 micron; 1.2 ps; 120 to 420 MHz; ADS simulation; DLL; TSMC CMOS process; circuit design; delay-locked loop; false locking problem; lock-detect circuit; CMOS process; Circuit simulation; Clocks; Delay effects; Delay lines; Detectors; Frequency; Jitter; Phase detection; Voltage; Clock Generator; DLL; PLL;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineering, 2006 3rd International Conference on
Conference_Location
Veracruz
Print_ISBN
1-4244-0402-9
Electronic_ISBN
1-4244-0403-7
Type
conf
DOI
10.1109/ICEEE.2006.251846
Filename
4017931
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