A programmable radar signal processor architecture

Author

Alter, James J. ; Evins, James B. ; Davis, Jennifer L. ; Rooney, Deborah L.

Author_Institution

US Naval Res. Lab., Washington, DC, USA

fYear

1991

fDate

12-13 Mar 1991

Firstpage

108

Lastpage

111

Abstract

A programmable radar signal processor architecture is described. It is designed to handle up to a 10-MHz analog/digital sample rate. The architecture consists of a front-end composed of a parallel array of programmable digital signal processing (DSP) devices, which performs the high-speed signal processing functions such as pulse compression, moving target indication, constant false alarm rate processing, etc., and outputs contact reports, to a back-end processor consisting of transputer microprocessors to perform post-detection processing. The processor is being developed to support the Point Defence Demonstration Radar

Keywords

digital signal processing chips; military computing; military systems; radar systems; transputers; 10 MHz; DSP devices; HF; Point Defence Demonstration Radar; alarm rate processing; analog/digital sample rate; architecture; back-end processor; constant false; contact reports; high-speed signal processing; military systems; moving target indication; parallel array; post-detection processing; programmable radar signal processor; pulse compression; transputer microprocessors; Digital signal processing; Digital signal processing chips; Digital signal processors; Field programmable gate arrays; Laboratories; Pulse compression methods; Radar signal processing; Signal processing; Signal processing algorithms; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Radar Conference, 1991., Proceedings of the 1991 IEEE National

Conference_Location

Los Angeles, CA

Print_ISBN

0-87942-629-2

Type

conf

DOI

10.1109/NRC.1991.114740

Filename

114740