• DocumentCode
    2744550
  • Title

    Next generation PowerPCTM microprocessor test strategy improvements

  • Author

    Pyron, Carol ; Prado, Javier ; Golab, James

  • Author_Institution
    Somerset Design Center, Motorola Inc., Austin, TX, USA
  • fYear
    1997
  • fDate
    1-6 Nov 1997
  • Firstpage
    414
  • Lastpage
    423
  • Abstract
    The first PowerPC microprocessor in the new G3 generation of designs, the MPC750, incorporates new test strategy approaches to improve the product test quality, reliability, and debug, and to reduce the total time to market
  • Keywords
    built-in self test; computer testing; design for testability; elemental semiconductors; integrated circuit testing; integrated circuit yield; logic testing; microprocessor chips; production testing; reliability; silicon; BIST; DFT; G3 generation; IEEE test; MPC750; PowerPCTM microprocessor; Si; Si debugging; debugging; microprocessor testing; product test quality; redundancy; reliability; scan testing; time to market; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Manufacturing; Microprocessors; Silicon; System buses; System testing; Time to market;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1997. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-4209-7
  • Type

    conf

  • DOI
    10.1109/TEST.1997.639644
  • Filename
    639644
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2744550