A Runtime Reconfigurable Architecture for Viterbi Decoding

Author

Campos, Juan Manuel ; Cumplido, Rene

Author_Institution

Departamento de Ciencias Computacionales, Inst. Nacional de Astrofisica, Opt. y Electron., Puebla

fYear

2006

fDate

6-8 Sept. 2006

Firstpage

1

Lastpage

4

Abstract

This paper presents the design and implementation of a runtime reconfigurable architecture for Viterbi decoding with a high throughput rate suitable for software defined radio (SDR). SDR is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. The architecture can be reconfigured to decode convolutionally coded data with constraint lengths from 3 to 7 and code rates 1/2 and 1/3. Reconfiguration of the architecture does not require FPGA reprogramming. With a throughput of 70 Mbps, the proposed decoder is suitable for use in receiver architectures of 802.11a, 802.16, 3G and GSM

Keywords

Viterbi decoding; convolutional codes; radio receivers; reconfigurable architectures; software radio; 70 Mbit/s; SDR; Viterbi decoding; convolutionally coded data; receiver architecture; runtime reconfigurable architecture; software defined radio; Computer architecture; Convolutional codes; Decoding; Field programmable gate arrays; Physical layer; Reconfigurable architectures; Runtime; Software radio; Throughput; Viterbi algorithm; Reconfigurability; SDR; Viterbi Decoding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Electronics Engineering, 2006 3rd International Conference on

Conference_Location

Veracruz

Print_ISBN

1-4244-0402-9

Electronic_ISBN

1-4244-0403-7

Type

conf

DOI

10.1109/ICEEE.2006.251908

Filename

4017993