DocumentCode
2745361
Title
Reconfigurable Hardware Implementation of the Lenstra Factorization Algorithm
Author
Zapotecas-Martinez, Saul ; Mancillas-López, Cuauhtemoc ; Rodriguez-Henriquez, Francisco ; Cruz-Cortés, Nareli
Author_Institution
Dept. of Electr. Eng., CINVESTAV, Mexico City
fYear
2006
fDate
6-8 Sept. 2006
Firstpage
1
Lastpage
4
Abstract
In this paper we describe the main arithmetic building blocks needed for implementing the Lenstra factorization algorithm on a reconfigurable hardware platform. Lenstra´s method is utilized here for factorizing 32-bit composite numbers of the form n=pmiddotq, with p, q prime numbers. Our design was implemented on a Xilinx Virtex 2 FPGA device. It can operate at a maximum clock frequency of 87 MHz occupying a total of 6868 slices
Keywords
field programmable gate arrays; reconfigurable architectures; 87 MHz; Lenstra factorization algorithm; Xilinx Virtex 2 FPGA device; field programmable gate array; reconfigurable hardware platform; Arithmetic; Clocks; Computer science; Elliptic curves; Field programmable gate arrays; Frequency; Hardware; Interleaved codes; Public key cryptography; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineering, 2006 3rd International Conference on
Conference_Location
Veracruz
Print_ISBN
1-4244-0402-9
Electronic_ISBN
1-4244-0403-7
Type
conf
DOI
10.1109/ICEEE.2006.251939
Filename
4018024
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