DocumentCode :
2745453
Title :
A Room Temperature 0.1 /spl mu/m CMOS on SOI
Author :
Shahidi, G.G. ; Blair, C. ; Beyer, K. ; Bucelot, T. ; Buti, T. ; Chang, P.N. ; Chu, S. ; Coane, P. ; Comfort, J. ; Davari, B. ; Dennard, R. ; Furkay, S. ; Hovel, H. ; Johnson, J. ; Klaus, D. ; Kiewtniack, K. ; Logan, R. ; Lii, T. ; McFarland, P.A. ; Mazze
Author_Institution :
IBM Semiconductor Research and Development Center
fYear :
1993
fDate :
17-19 May 1993
Firstpage :
27
Lastpage :
28
Abstract :
An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick non- delpleted (0.1 /spl mu/m) SOI film, highly non-uniforin channel doping and source-drain extension-HALO were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. Very high speeds were obtained: Unloaded delay was 20 psec, and fully loaded NAND (FI=FO=3, CL-0.3 pF) delay was 130 psec at supply of 1.8 V.
Keywords :
CMOS integrated circuits; Delays; Doping; Films; Logic gates; MOS devices; Semiconductor process modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
Type :
conf
DOI :
10.1109/VLSIT.1993.760228
Filename :
760228
Link To Document :
بازگشت