DocumentCode
2745770
Title
A Low cost, microprocessor compatible, 18.4 um/sup 2/,6-t bulk cell technology for high speed SRAMS
Author
Helm, M. ; Kavanaugh, W. ; Liew ; Petti, C. ; Stolmeijer, A. ; Ben-tzur, M. ; Bornstein, J. ; Lilygren, J. ; Ting, W. ; Trammel, P. ; Allan, J. ; Gray, G. ; Hartranft, M. ; Radigan, S. ; Shanmugan, J.K. ; Shrivastava, R.
Author_Institution
Cypress Semiconductor Corp.
fYear
1993
fDate
17-19 May 1993
Firstpage
65
Lastpage
66
Abstract
A unique low cost, microprocessor compatible, 0.5 /spl mu/m/sup 2/ 5V CMOS technology utilizing an 18.4 4m2 bulk 6T cell for high density, high speed SRAMs is described. Microprocessor compatibility is ensured by improving CMOS and inter-onnect area efficiency. A 256K SRAM is used to demonstrate the technology.
Keywords
CMOS integrated circuits; Complexity theory; Layout; Metals; Random access memory; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location
Kyoto, Japan
Type
conf
DOI
10.1109/VLSIT.1993.760247
Filename
760247
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