DocumentCode
2746034
Title
A High Performance 0.25/spl mu/m CMOS
Author
Shahidi, C.G. ; Warnock, J. ; Acovic, A. ; Agnello, P. ; Blair, C. ; Bucelot, T. ; Burghartz, A. ; Crabbe, E. ; Cressler, J. ; Coane, P. ; Comfort, J. ; Davari, B. ; Fischer, S. ; Canin ; Gittleman, S. ; Keller, J. ; Jenkins, K. ; Klaus, D. ; Kiewtniak, K
Author_Institution
IBM Semiconductor Research and Development Center
fYear
1993
fDate
17-19 May 1993
Firstpage
93
Lastpage
94
Abstract
In this paper a CMOs technology with the nominal channel length of 0.15 Am and minimum channel length below 0.1 /spl mu/m is presented. Loaded NAND (FI=FO=3, CL=240 fF) delay of 200 psec and unloaded delay of 33 psec at supply voltage of 1.8 V is demonstrated. In order to minimize short channel effects down to channel length below 0.1 /spl mu/m, highly non-uniform channel doping obtained by indium and antimony, and source-drain extensions were utilized. To minimze the gate RC, a polycide s stack gate structure was used.
Keywords
CMOS integrated circuits; CMOS technology; Delays; Doping; Junctions; Logic gates; MOS devices;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location
Kyoto, Japan
Type
conf
DOI
10.1109/VLSIT.1993.760261
Filename
760261
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