A triple-controlled DDS-based PLL for 3 to 4 GHz frequency synthesis

In this paper, a triple-controlled direct digital synthesis (DDS)-based phase-locked loop (PLL) for 3 to 4 GHz frequency synthesis is presented. The architecture has the merits of low spurs, a fast switching speed and high frequency resolution. It corrects the output of DDS and changes the division ratios of two variable frequency dividers in PLL to avoid high level spurs falling in the loop bandwidth of PLL. The additional DAC output is added to the output of the loop filter to drive the VCO. It provides the PLL with a fast switching speed. Experiment and measurement results showed that this type of frequency synthesizer architecture has better performance than conventional PLL and can be used in most applications of frequency synthesis.