An integration of polyphase filter and polyphase mixer architecture for high-speed DDC

In this paper, a new architecture is proposed for high-speed digital down conversion (DDC) for communication signal processing. The proposed architecture integrates conventional polyphase filter with polyphase mixer (PFPM) for decimation in DDC. The PFPM architecture decreases both the rate of the mixer and filter and can process the signals with a very high sample rate, which cannot be realistically implement in conventional DDC in a general purpose processor (GPP) such as field programmable gate array (FPGA) or digital signal processor (DSP). Simulation and experiment have been done to verify the availability of the PFPM architecture. These results show that the proposed PFPM architecture reduces the operation rate of the mixer and well agrees with the conventional DDC architecture.