Realization of area efficient QR factorization using unified division, square root, and inverse square root hardware

The QR factorization is used in many signal processing and communication applications such as echo cancellation, adaptive beamforming and multiple-input-multiple-output (MIMO) systems. However, division, square root and inverse square root operations required by the QR algorithm are very difficult to implement because they are computationally slow and area-consuming arithmetic operations. This paper presents unified hardware architecture for fast, area efficient QR factorization based on the Householder transformation. Newton-Raphson, and Goldschmidt algorithms are used for fast division, square root and inverse square root blocks. By using a unified architecture, area and power requirements for QR factorization are reduced without decreasing overall speed. The design and implementation of the proposed hardware is presented with synthesis results based on FPGA hardware.