New Converter Architectures with Multi-interleaving Technique for Future Microprocessors

In low voltage and high current application, specially for future microprocessors, there is a serious challenge to present voltage regulators with high efficiency, high power density, fast transient response and low-cost. As previously identified, multiphase interleaving buck converter is not enough to meet the power challenges because the technical conflicts of duty cycle and switching frequency impair the efficiency. In this paper, new converter architectures with multi-interleaving technique are proposed to remove the technical conflicts. Multiphase buck converters with multi-interleaving technique perform better than with interleaving technique because the multi-interleaving technique can improve current ripple cancellation effect. Moreover, the multi-interleaving technique can extend duty cycle, can improve transient response without increasing current ripple in each cell, and can raise the switching frequency with low switching, gate drive and body diode losses. Losses analysis and simulation results show that the proposed converter architectures provide an opportunity to resolve the power challenges. As a result, extending Moore´s Law without increasing power consumption can be realized