Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology

This paper describes a design and implementation of low-power and high-speed security hardware cores for the advanced encryption standard (AES) and the secure hash algorithm (SHA1). We propose three register transfer level (RTL) circuit techniques, namely, application specific register reduction (ASRR), locally explicit clock enabling (LECE), and bus specific clock (BSC). LECE and BSC can be used directly to any ASIC design flow and can be applied for any technology nodes. With 65 nanometer industry technology, our proposed schemes demonstrated at RTL and gate level that for AES, 44.57% total power reduction (dynamic and cell leakage power), 10.43% area reduction, and 5.78 Gbps throughput with 452 MHz circuit speed are achieved and for SHA1, 63.26% total power reduction, 12.72% area reduction with 1.28 GHz circuit speed are achieved.