DocumentCode :
2748316
Title :
Fast memory addressing scheme for radix-4 FFT implementation
Author :
Xiao, Xin ; Oruklu, Erdal ; Saniie, Jafar
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear :
2009
fDate :
7-9 June 2009
Firstpage :
437
Lastpage :
440
Abstract :
In this study, an efficient addressing scheme for radix-4 FFT processor is presented. The proposed method uses extra registers to buffer and reorder the data inputs of the butterfly unit. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 FFT implementations. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. For performance evaluation, the new FFT architecture has been implemented by FPGA (Altera Stratix) hardware and also synthesized by CMOS 0.18 mum technology. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix FFT.
Keywords :
CMOS integrated circuits; fast Fourier transforms; field programmable gate arrays; microprocessor chips; CMOS technology; FPGA hardware; address generator; fast Fourier transform; fast memory addressing scheme; field programmable gate arrays; radix-4 FFT processor; size 0.18 mum; CMOS technology; Counting circuits; Discrete Fourier transforms; Fast Fourier transforms; Field programmable gate arrays; Flexible printed circuits; Hardware; Multiplexing; Pipeline processing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electro/Information Technology, 2009. eit '09. IEEE International Conference on
Conference_Location :
Windsor, ON
Print_ISBN :
978-1-4244-3354-4
Electronic_ISBN :
978-1-4244-3355-1
Type :
conf
DOI :
10.1109/EIT.2009.5189656
Filename :
5189656
Link To Document :
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