Title :
Micro-architectural power estimation and optimization
Author :
Hidaji, Babak ; Andalibizadeh, M.R. ; Alipour, Salar
Author_Institution :
Comput. Sci. & Eng. Dept., Chalmers Univ. of Technol., Gothenburg, Sweden
Abstract :
Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit´s MTBF on high temperature and cooling difficulties. It is investigated that only 30% improvement in battery performance will be obtained in five years. This paper is an overview on power estimation and optimization researches and the overall flow of presenting the information is based on the reference. We review the architectural template and the methods to provide model for power consumption of different types of components. Some common optimization techniques including clock-gating, exploiting the common case of the design and managing voltage are being reviewed.
Keywords :
CMOS digital integrated circuits; optimisation; battery performance; clock-gating; digital CMOS circuit; microarchitectural power estimation; optimization techniques; Buildings; Capacitance; Clocks; Design optimization; Energy consumption; Equations; Power dissipation; Remuneration; Sequential circuits; Structural engineering;
Conference_Titel :
Electro/Information Technology, 2009. eit '09. IEEE International Conference on
Conference_Location :
Windsor, ON
Print_ISBN :
978-1-4244-3354-4
Electronic_ISBN :
978-1-4244-3355-1
DOI :
10.1109/EIT.2009.5189658
