DocumentCode :
2748374
Title :
On-line testing scheme for clock´s faults
Author :
Metra, Cecilia ; Favalli, Michele ; Riccò, Bruno
Author_Institution :
Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
fYear :
1997
fDate :
1-6 Nov 1997
Firstpage :
587
Lastpage :
596
Abstract :
This paper proposes an on-line testing scheme for permanent and temporary faults which affect signals of the clock distribution network of synchronous systems, and which make them stuck-at, or change with incorrect frequency or duty-cycle. By means of straightforward modifications, the proposed scheme can be also used to detect on-line undesired skews between couples of clock signals
Keywords :
VLSI; automatic testing; clocks; fault diagnosis; integrated circuit testing; timing; VLSI; clock distribution network; clock faults; clock signal coupling; duty-cycle; on-line testing scheme; on-line undesired skews; permanent faults; synchronous systems; temporary faults; Circuit faults; Circuit testing; Clocks; Crosstalk; Digital systems; Electrical fault detection; Fault detection; Logic testing; System testing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-4209-7
Type :
conf
DOI :
10.1109/TEST.1997.639667
Filename :
639667
Link To Document :
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