Performance evaluation of SRAM cells in 22nm predictive CMOS technology

Static Random Access Memory (SRAM) units are often directly integrated onto the same die with the microprocessors and influence the design metrics significantly. SRAM often consumes large percentages of the die size and their leakages significantly contribute to the static power dissipation of those chips. The main objective of this article is to characterize the speed and power consumption of five different SRAM cells in a predictive high performance 22 nm transistor process and in a predictive low power 22 nm transistor process. The five types of studied cells are traditional 6T, gated-ground 7T, full Self- Controlled Voltage Level (SVL) 12T, SVL 9T Footed, and SVL 9T Headed. The simulation results indicate that the timing behavior of SRAM cells are largely the same but power dissipation, leakage power in particular, vary significantly in 22 nm technology. The gated-ground 7T cells are deemed superior in the high performance process, while traditional 6T cells are deemed the best in the low power process.