Title :
System level boundary scan in a highly integrated switch
Author :
Hughes, William J., III
Author_Institution :
Gen. Signal Networks, Mt. Laurel, NJ, USA
Abstract :
JTAG and continuity testing can only go so far at a board or module testing level. When all of the pieces come together, employing boundary scan (IEEE 1149.1) techniques at a system level can significantly reduce the time it takes to test a large product with literally thousands of interconnections. Although there are many benefits to system level JTAG, there are pitfalls as well. This paper describes an experience of implementing system level boundary scan in a highly integrated switch
Keywords :
boundary scan testing; electronic switching systems; telecommunication equipment testing; telecommunication standards; IEEE 1149.1; boundary scan techniques; integrated switching systems; system level; system level boundary scan; Assembly; Backplanes; Connectors; Electronics packaging; Intelligent networks; Logic testing; Switches; Switching systems; System testing; Very large scale integration;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639673
