A self-timed, pipelined floating point FFT processor architecture

This paper presents the self-timed design of 8-point pipeline floating point FFT processor. The self-timed technique is used to overcome global clock overhead and distribution problem in synchronous FFT processors due to large area size of floating point arithmetic units. The self-timed floating point adder, complex multiplier and butterfly computation units are designed. The hardware reduction approach is performed by using the single shift registers instead of barrel shift switches in floating point adders by self-timed techniques, which introduces the dependency of FFT processor response time on input data stream.