Title :
Performance Evaluation and ASIC Design of LDPC Decoder for IEEE802.11n
Author :
Syafei, W.A. ; Yohena, R. ; Shimajiri, H. ; Yoshida, T. ; Kurosaki, M. ; Nagao, Y. ; Sai, B. ; Ochi, H.
Author_Institution :
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka
Abstract :
This paper presents our investigation on performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system and its Application Specific Integrated Circuit design. Simulation result shows that in higher coding rate, LDPC codes gives 6 dB better performance compared to binary convolutional codes. Logic synthesis is succesfully done on 0.13 mum CMOS technology with low-power standard cell library.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; decoding; parity check codes; wireless LAN; ASIC design; CMOS technology; IEEE802.11; LDPC decoder; application specific integrated circuit design; binary convolutional codes; logic synthesis; low density parity check codes; low-power standard cell library; size 0.13 mum; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Circuit simulation; Convolutional codes; Decoding; Integrated circuit synthesis; Integrated circuit technology; Libraries; Parity check codes;
Conference_Titel :
Consumer Communications and Networking Conference, 2009. CCNC 2009. 6th IEEE
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-2308-8
Electronic_ISBN :
978-1-4244-2309-5
DOI :
10.1109/CCNC.2009.4784735
