DocumentCode :
2750852
Title :
A novel variable grain logic cell architecture with multifunctionality
Author :
Yamaguchi, Ryo ; Amagasaki, Motoki ; Matsuyama, Kimihide
Author_Institution :
Kumamoto Univ., Kumamoto
fYear :
2007
fDate :
Oct. 30 2007-Nov. 2 2007
Firstpage :
1
Lastpage :
4
Abstract :
Reconflgurable logic devices are usually classified on the basis of their basic logic cell architecture as fine-grained or coarse-grained type. The coarse-grained architecture is suitable for byte-level processing. On the other hand, the fine-grained architecture is suitable for bit-level processing. The granularity of each type is fixed; therefore, it is difficult to achieve a balance between the operation speed and area efficiency in applications. To overcome this problem, we proposed a variable grain logic cell (VGLC) architecture that can change the operation granularity depending on each application. The VGLC has various functions to achieve both high flexibility and performance. In this paper, we map benchmark designs on the VGLC and compare with it commercial FPGAs. As a result, we show that the proposed architecture improves to cover a maximum 55% of the implementation area.
Keywords :
field programmable gate arrays; logic devices; bit-level processing; byte-level processing; coarse-grained architecture; fine-grained architecture; reconflgurable logic devices; variable grain logic cell architecture; Adders; Arithmetic; Circuits; Computer architecture; Energy consumption; Field programmable gate arrays; Logic devices; Reconfigurable architectures; Reconfigurable logic; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2007 - 2007 IEEE Region 10 Conference
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1272-3
Electronic_ISBN :
978-1-4244-1272-3
Type :
conf
DOI :
10.1109/TENCON.2007.4428818
Filename :
4428818
Link To Document :
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