New Circular-Carry-Select (CCS) architecture for diminished-one modulo 2n+1 addition

Abstract-The diminished-one modulo 2ⁿ+l addition is an important arithmetic operation for a high-performance residue number system (RNS). In this paper, we propose a new Circular-Carry-Select (CCS) architecture for diminished-one modulo 2ⁿ+l adder. The resulting modulo 2"+l adder is mainly based on CCS addition block which is simple and regular for all n values. For actual VLSI implementation based on UMC 180 nm CMOS technology, the CCS-based diminished-one modulo 2ⁿ+l adder demonstrates the superiority in AreaxTime (AT) performance over those of the famous existing solutions. The area and clock rate for CCS-based modulo 2¹⁶+1 adder chip are 26746 mum² and 476 MHz respectively.