DocumentCode :
2751156
Title :
Incorporating physical design-for-test into routing
Author :
McGowen, Richard ; Ferguson, F. Joel
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fYear :
1997
fDate :
1-6 Nov 1997
Firstpage :
685
Lastpage :
693
Abstract :
In addition to automatically generating correct wiring, routers are used to meet additional design goals. Examples include reducing capacitive coupling and improving yield. Using routers to improve testability has been mentioned in the literature, but concrete rules or methods have not been explained or implemented. In this paper, we show how a modified router improves bridge fault testability for two different test metrics, static-voltage testing and pseudo-exhaustive segmentation testing, with no significant increase in area or time. This method is flexible in that further testability improvements are possible by trading off routing area or routing time
Keywords :
automatic testing; circuit layout CAD; design for testability; fault location; integrated circuit testing; iterative methods; probability; voltage measurement; bridge fault testability; capacitive coupling; design-for-test; modified router; pseudo-exhaustive segmentation testing; routing area; routing time; static-voltage testing; testability; wiring; Bridge circuits; Circuit faults; Circuit testing; Design for testability; Educational institutions; Integrated circuit testing; Output feedback; Routing; Wires; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
ISSN :
1089-3539
Print_ISBN :
0-7803-4209-7
Type :
conf
DOI :
10.1109/TEST.1997.639681
Filename :
639681
Link To Document :
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